Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, operate with a lower voltage, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
Power MOSFETs are one example of semiconductor devices commonly used in electronic circuits, such as communication systems and power supplies. Power MOSFETs are particularly useful when used as electric switches to enable and disable the conduction of relatively large currents. The on/off state of the power MOSFET is controlled by applying and removing a triggering signal at the gate electrode. When turned on, the electric current in the MOSFET flows between the drain and source. When turned off, the electric current is blocked by the MOSFET.
The miniaturization of power MOSFETs produces devices that include small MOSFET cells or transistors that are distributed across an entire surface of a semiconductor die. MOSFET cells include source and drain regions that are formed at the scale of electrical interconnects, such as bumps formed over source and drain pads, or terminals, for subsequent electrical interconnect. Accordingly, multiple source and drain regions are often located under a single source or drain pad. The use of strictly vertical interconnects within a power MOSFET with closely spaced transistors does not provide for connecting both source and drain regions of a transistor located under a single source pad or drain pad to connect with corresponding horizontally offset source pads and drain pads. Accordingly, an interconnect structure that accounts for horizontal offset is needed to connect source and drain regions located under a single source or drain pad to horizontally offset source and drain pads.
Furthermore, power MOSFETs, like other semiconductor devices, include interconnect structures for electrically connecting the semiconductor device to substrates, circuit boards, and other semiconductor devices. One common technique of interconnecting a semiconductor die with a printed circuit board (PCB) or other device involves the use of solder bumps. FIG. 1a shows a conventional UBM solder bump structure 10. Solder bump structure 10 includes a semiconductor die 11 including a semiconductor wafer of base silicon 12 over which an active area 14 is formed. Active area 14 includes analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within semiconductor die 11 and electrically interconnected according to the electrical design and function of the semiconductor die. An electrically conductive layer 16 is formed over active area 14 of semiconductor die 11, and operates as a contact pad. An insulation or passivation layer 18 is formed over semiconductor die 11 and conductive layer 16. A portion of insulation layer 18 is removed by an etching process to form opening 20 in the insulation layer that exposes a portion of conductive layer 16. In one embodiment, opening 20 has a width of 270 micrometers (μm). An electrically conductive or UBM layer 22 is formed over, and conformally applied to, conductive layer 16, within opening 20, and over a portion of insulation layer 18. In one embodiment, conductive layer 22 includes an adhesion layer, barrier layer, and wetting layer comprising aluminum (Al), nickel vanadium (NiV), and copper (Cu), respectively. An insulation or passivation layer 24 such as benzocyclobutene (BCB) is formed over conductive layer 22 and insulation layer 18. An opening 26 in insulation layer 24 is formed over and exposes a portion of UBM 22. In one embodiment, opening 26 has a width of 280 μm. A conductive bump 28 is disposed over conductive layers 16 and 22, and within openings 20 and 26 to complete conventional UBM solder bump structure 10. In one embodiment, conductive bump 28 includes a preformed solder sphere with a predetermined diameter 30 of 350 μm that is mounted to conductive layer 22 in a ball drop process.
FIG. 1b shows semiconductor die 11 with the conventional UBM solder bump structure 10 from FIG. 1a packaged as part of an over molded system in package (SiP) 32. Semiconductor die 11 is mounted to substrate or multilayered PCB 34 which further includes conductive contacts 36. Underfill 38 is deposited around bumps 28 and between substrate 34 and active area 14 of semiconductor die 11 to improve a connection between semiconductor die 11 and substrate 34. Bumps 28 undergo multiple reflows to improve electrical and mechanical connections. The multiple reflows of bumps 28 include reflowing bumps 28 for connecting the bumps to semiconductor die 11, reflowing bumps 28 while connected to semiconductor die 11 to connect semiconductor die 11 and bumps 28 to substrate 34, reflowing bumps 28 when mounting SiP 32 to an additional substrate or multilayered PCB, and reflowing bumps 28 for the mounting of additional components to, or rework of, the additional substrate or multi-layered PCB. However, reflowing bumps 28 in some instances leads to solder bridging and electrical shorting among bumps 28, thereby causing failure of semiconductor die 11. Solder bridging and electrical shorting among bumps 28 is more likely to occur when the bumps have a fine pitch. Underfill material 38 is optimized to prevent voiding of the underfill between bumps 28 and to help prevent solder bridging and electrical shorting by keeping bump material localized during reflow. However, controlling placement of underfill material 38 is difficult and may result in the placement of the underfill with a non-uniform thickness. A non-uniform thickness of underfill material 38 is common and includes, for example, a configuration in which only a portion of a gap between semiconductor die 11 and substrate 34 on a first side of the semiconductor die is filled while an entirety of the gap on a second side of the semiconductor die is filled. Unevenly distributed underfill 38 causes an imbalance of stresses on semiconductor die 11 which can lead to cracking and failure of the semiconductor die. Furthermore, encapsulant or mold compound 40 is placed over and around semiconductor die 11. The combination of encapsulant 40 and unevenly distributed underfill 38 further causes an imbalance of stresses on semiconductor die 11, which further leads to cracking and failure of the die. Accordingly, the conventional assembly of SiP 32 with underfill 38 is prone to defects that decrease the yield and reliability of the SiP assemblies.